TP 10.5: A 13.4-GHz CMOS Frequency Divider

The above difficulty is alleviated by use ofring-shaped transistors, where the ratio of device width and drain junction capacitance is approximately four times that of a regular layout [4]. However, such a structure proves b neficial if only oneofthedrainorsourceterminalsappearsinthesignalpath. Thus, high-speed divider topologies using stacked devices or pass gates do not necessarily achieve a higher speed if they incorporate this structure. Another drawback of typical divider topologies stems from their use of PMOS devices in the critical signal path. The transconductance-input capacitance trade-off of these transistors degrades speed significantly.